This invention relates to semiconductor devices for information storage. In particular, the invention relates to a multi-layer memory device for a random access memory and to methods of fabrication of such a memory.
Various dynamic random access memory (DRAM) semiconductor cell structures have been proposed using thyristors. The assignee herein describes several thyristor semiconductor structures for DRAMs, and the processes for manufacturing them in two as well as three-dimension arrays in various commonly assigned co-pending patent applications. See, e.g., the provisional patent applications cited above. This application describes improvements over the technology described in those applications.
The 1-transistor 1-capacitor memory cell has been by far the predominant memory cell used in DRAM devices for the last 30 years. Bit density has quadrupled approximately every 3 years by lithographical scaling and ever increasing process complexity. Maintaining the capacitance value and low transistor leakage, however, are significant issues for further reductions in cell area.
Recently alternative DRAM cells have been proposed to overcome the scaling challenges of conventional DRAM technology. These include floating body DRAM (FBDRAIVI), a single MOSFET built on either a silicon-on-insulator (Okhonin, Int. SOI Conf., 2001) or in triple-well with a buried n-implant (Ranica, VLSI Technology, 2004). These technologies have yet to solve data retention issues, particularly in small geometry cells.
Various cell designs have been proposed based on the negative differential resistance behavior of a thyristor. An active or passive gate is often used in these designs to optimize trade-offs among switching speed, retention leakage, and operation voltage. The thin capacitively coupled thyristor disclosed in U.S. Pat. No. 6,462,359 is a lateral pnpn thyristor constructed on a silicon on insulator substrate with a coupling gate for increased switching speed.
Liang in U.S. Pat. No. 9,013,918 disclosed a pnpn thyristor cell that is constructed on a silicon substrate and operated in forward and reverse breakdown region for writing data into the cell. The use of epitaxial or CVD semiconductor layers at the backend of the standard CMOS process, add-on thermal cycles and etch steps, however, degrade performance and yield of devices already formed on, or in, the substrate. In addition, pnpn devices operated in the breakdown regime pose challenges in process control and power consumption.
Recently, Kim et al. reported electrical characteristics for a thyristor based memory in “Design and Electrical Characterization of 2-T Thyristor RAM with Low Power Consumption,” IEEE Electron Device Letters, volume 39, issue 3, Jan. 23, 2018.